The present invention relates to a method and/or architecture for an electrical identification (ID) generally and, more particularly, to a method and/or architecture for an electrical ID that may operate in conjunction with existing circuitry.
An electrical ID may be needed during product qualification so that information such as (i) the wafer location of test or qualification failures, (ii) the circuit power supply voltage, (iii) wafer lot number can be identified (iv) other pertinent information. To indicate the electrical ID of a circuit, the status (i.e., blown or unblown) of a fuse or fuses within the circuit may be determined. Several conventional methodologies of electrical ID are currently employed. For electrical ID of input pads, a diode stack is connected to the input pad. If a particular fuse is unblown, a specified number of diode drops are measured when current is forced into the input. If the particular fuse is blown, a different number of diode drops are measured.
Some devices do not have enough input pads for full electrical ID. In particular, certain devices are implemented with bi-directional address ports in place of input pads. Such devices may have an insufficient number of input pads to implement a full electrical ID. A diode stack generally cannot be used for electrical ID on an output pad. The PMOS transistor drain diode in an output pad can mask the diode stack used for standard electrical ID because the turn on voltage of the transistor drain diode is lower than the diode stack.
For electrical ID using output pads, conventional approaches use a parallel in, serial out, shift register. The parallel input of the shift register is connected to a fuse bank. The shift register is used to serially shift out the status of the fuses. The use of a shift register is cumbersome and complex. The use of a parallel in, serial out, shift register is time consuming since the fuse status is read out serially.
Programmable Logic Devices (PLD) are sometimes implemented with extra programmable memory cells to store electrical ID data. Such additional cells have the disadvantage of increased cost, board area, etc.
The present invention concerns an apparatus for electrical identification comprising a first circuit and a second circuit. The first circuit may be configured to generate a first output signal in response to one or more first input signals. The second circuit may be configured to generate a second output signal in response to one or more second input signals. The first and second output signals may be presented to a bond pad.
The objects, features and advantages of the present invention include providing a method and/or architecture for implementing an electrical identification that may (i) be implemented on an input, output, and/or I/O bond pad, (ii) be implemented without a diode stack, (iii) retain the original speed of an output path, and/or (iv) provide an electric identification that may be a voltage level driven by the device tested.